Processors, including microprocessors, digital signal processors and microcontrollers, operate by running software programs that are embodied in one or more series of instructions stored in a memory. The processors run the software by fetching the instructions from the series of instructions, decoding the instructions and executing them. The instructions themselves control the order in which the processor fetches and executes the instructions. For example, the order for fetching and executing each instruction may be inherent in the order of the instructions within the series. Alternatively, instructions such as branch instructions, conditional branch instructions, subroutine calls and other flow control instructions may cause instructions to be fetched and executed out of the inherent order of the instruction series.
When a processor fetches and executes instructions in the inherent order of the instruction series, the processor may execute the instructions very efficiently without wasting processor cycles to determine, for example, where the next instruction is. When exceptions to normal instruction flow such as interrupts are processed, many processor cycles are taken away from the normal instruction flow to process an interrupt service routing (ISR) corresponding to the interrupt or exception.
In processor applications in which real-time performance of the processor is critical, there is a need to regulate when an interrupt is serviced in order to prevent impairing the real-time performance of the processor. The need may arise at only certain portions of a larger program, for example, when monitoring and processing operations are being performed. At these times, there is a need for a mechanism to prevent the servicing of an interrupt in order to devote processing power to processing the critical program portions.